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M366S3323DTS
M366S3323DTS SDRAM DIMM
PC133/PC100 Unbuffered DIMM
32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION
The Samsung M366S3323DTS is a 32M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S3323DTS consists of sixteen CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M366S3323DTS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
* Performance range Part No. M366S3323DTS-C/L7C M366S3323DTS-C/L7A M366S3323DTS-C/L1H M366S3323DTS-C/L1L * * * * * Max Freq. (Speed) 133MHz (7.5ns @ CL=2) 133MHz (7.5ns @ CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * PCB : Height (1,375mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 VSS NC NC VDD WE DQM0 Front Pin Front Pin DQ18 DQ19 VDD DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC **SDA **SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 *CB4 *CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 *A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 VDD 29 DQM1 57 58 CS0 30 59 31 DU 60 32 VSS 61 33 A0 62 34 A2 63 35 A4 64 36 A6 65 37 A8 38 A10/AP 66 67 39 BA1 68 40 VDD 69 41 VDD 42 CLK0 70 71 43 VSS 72 44 DU 73 45 CS2 46 DQM2 74 47 DQM3 75 76 48 DU 77 49 VDD 78 50 NC 79 51 NC 52 *CB2 80 53 *CB3 81 82 54 VSS 55 DQ16 83 56 DQ17 84
PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK3 CS0 ~ CS3 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF SDA SCL SA0 ~ 2 DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Dont use No connection
CKE0 ~ CKE1 Clock enable input
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001
M366S3323DTS
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
PC133/PC100 Unbuffered DIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 VDD/VSS
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
Rev. 0.1 Sept. 2001
M366S3323DTS
FUNCTIONAL BLOCK DIAGRAM
CS1 CS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS3 CS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 ~ An, BA0 & 1 RAS CAS WE CKE0 10 DQn VDD Vss * * * * Two 0.1uF Capacitors per each SDRAM To all SDRAMs Every DQpin of SDRAM * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 *
PC133/PC100 Unbuffered DIMM
DQM4 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 CS CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
* DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
U0
U8
U4
U12
U1
U9
DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7
DQM CS DQ0 DQ1 DQ2 U13 DQ3 DQ4 DQ5 DQ6 DQ7
* DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
* CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
* DQM6 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
Serial PD SCL 47K WP A0 SDA A1 A2
CS
U2
U10
U6
DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U14
CS
CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CS
U3
U11
U7
U15
SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U7 CKE1 * 10K SDRAM U8 ~ U15 VDD
SA0 SA1 SA2
10 CLK0/1/2/3
* * * * 3.3pF
U0/U1/U2/U3 U4/U5/U6/U7 U8/U9/U10/U11 U12/U13/U14/U15
Rev. 0.1 Sept. 2001
M366S3323DTS
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS
PC133/PC100 Unbuffered DIMM
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 16 50 Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Pin Symbol CADD CIN CCKE CCLK CCS CDQM COUT Min 45 45 25 15 15 10 13 Max 85 85 45 21 25 15 18 Unit pF pF pF pF pF pF pF
Address (A0 ~ A11, BA0 ~ BA1) RAS, CAS, WE CKE (CKE0 ~ CKE1) Clock (CLK0 ~ CLK3) CS (CS0 ~ CS3) DQM (DQM0 ~ DQM7) DQ (DQ0 ~ DQ63)
Rev. 0.1 Sept. 2001
M366S3323DTS
DC CHARACTERISTICS
PC133/PC100 Unbuffered DIMM
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Test Condition - 7C Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P ICC2PS ICC2N Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode Active standby current in non power-down mode (One bank active) ICC3P ICC3PS ICC3N ICC3NS 1040 Version -7A 960 32 32 320 mA 160 80 80 480 400 mA mA -1H 960 -1L 960 mA 1 Unit Note
mA
mA
Operating current (Burst mode) Refresh current Self refresh current
ICC4
1120
1120
1040
1040
mA
1
ICC5 ICC6
2000
1840 32
1760
1760
mA mA
2
12.8
Rev. 0.1 Sept. 2001
M366S3323DTS
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
PC133/PC100 Unbuffered DIMM
Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Unit V V ns V
1200 Output 870 * * * 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50 *
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol - 7C tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 60 65 2 2 CLK + tRP 1 1 1 2 1 15 15 15 45 15 20 20 45 100 70 70 Version - 7A - 1H 20 20 20 50 -1L 20 20 20 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Sept. 2001
M366S3323DTS
PC133/PC100 Unbuffered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 2.5 2.5 1.5 0.8 1 5.4 5.4 tSAC Symbol Min tCC 7.5 7.5 5.4 5.4 3 3 2.5 2.5 1.5 0.8 1 5.4 6 - 7C Max 1000 Min 7.5 10 5.4 6 3 3 3 3 2 1 1 6 6 - 7A Max 1000 Min 10 10 6 6 3 3 3 3 2 1 1 6 7 ns ns ns ns ns ns 3 3 3 3 2 - 1H Max 1000 Min 10 12 6 7 ns 2 ns 1,2 - 1L Max 1000 ns 1 Unit Note
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.1 Sept. 2001
M366S3323DTS
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS
PC133/PC100 Unbuffered DIMM
A11, A9 ~ A0
RAS
CAS
WE
DQM
BA0,1
A10/AP
Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A9) Column address (A0 ~ A9)
3 3
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.1 Sept. 2001
M366S3323DTS
PACKAGE DIMENSIONS
PC133/PC100 Unbuffered DIMM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100)
1.375 (34.925)
0.118 (3.000)
.118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890)
A 0.250 (6.350) .450 (11.430) 1.450 (36.830)
B 0.250 (6.350)
C
2.150 (54.61) 4.550 (115.57)
0.100 Min (2.540 Min)
0.700 (17.780)
0.150 Max (3.81 Max) (4.19 Min) 0.165 Min
0.050 0.0039 (1.270 0.10)
(2.540 Min)
0.100 Min
0.250 (6.350)
0.250 (6.350)
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
Detail A
Detail B
Detail C
Tolerances : .005(.13) unless otherwise specified The used device is 16Mx8 SDRAM, TSOP SDRAM Part No. : K4S280832D
Rev. 0.1 Sept. 2001
M366S3323DTS
* * * * * * * *
PC133/PC100 Unbuffered DIMM
M366S3323DTS-L7C/L7A/L1H/L1L,C7C/C7A/C1H/C1L (Intel SPD 1.2B ver. base)
Organization : 32Mx64 Composition : 16Mx8 *16 Used component part # : K4S280832D-TL7C/TL75/TL1H/TL1L,TC7C/TC75/TC1H/TC1L # of rows in module : 2 Row # of banks in component : 4 banks Feature : 1,375mil height & double sided component Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described -7C # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuraion type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 2&3 7.5ns 5.4ns Function Supported -7A -1H -1L -7C Hex value -7A 80h 08h 04h 0Ch 0Ah 02h 40h 00h 01h 10ns 6ns 75h 54h 75h 54h 00h 80h 08h 00h 01h 8Fh 04h 2&3 06h 06h 01h 01h 00h 06h 06h A0h 60h A0h 60h 2 2 1 1 -1H -1L Note
128bytes 256bytes (2K-bit) SDRAM 12 10 2 row 64 bits LVTTL 7.5ns 5.4ns 10ns 6ns
Non parity 15.625us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 2&3
0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
Burst Read Single bit Write precharge all, auto precharge 7.5ns 5.4ns 10ns 6ns 15ns 15ns 15ns 45ns 20ns 15ns 20ns 45ns 20ns 20ns 20ns 50ns 20ns 20ns 20ns 50ns 0Fh 0Fh 0Fh 2Dh 14h 0Fh 14h 2Dh 10ns 6ns 12ns 7ns 75h 54h A0h 60h
0Eh A0h 60h 00h 00h 14h 14h 14h 32h 20h 14h 14h 14h 32h C0h 70h 2 2
2 row of 128MB 1.5ns 0.8ns 1.5ns 1.5ns 0.8ns 1.5ns 2ns 1ns 2ns 2ns 1ns 2ns 15h 08h 15h 15h 08h 15h
20h 10h 20h
20h 10h 20h
Rev. 0.1 Sept. 2001
M366S3323DTS
Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described -7C Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Year) Manufacturing date (Week) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations 7 C 0.8ns
PC133/PC100 Unbuffered DIMM
Function Supported -7A 0.8ns Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 3 3 2 3 D T S "-" L/C 7 A Blank S D-die (5th Gen.) Undefined 100MHz Detailed PC100 Information Undefined FFh FFh 1 H 1 L 37h 43h 6Fh B0h CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 33h 33h 32h 33h 44h 54h 53h 2Dh 4Ch/43h 37h 41h 20h 53h 44h 64h FFh FDh 3 3 4 31h 48h 31h 4Ch -1H 1ns -1L 1ns -7C 08h Hex value -7A 08h 00h 12h 17h 47h -1H 10h -1L 10h Note
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
Rev. 0.1 Sept. 2001

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